As the frequencies of modern computers continue to increase, the need to rapidly transmit data between chip interfaces also increases. To accurately receive data, a clock is often sent to help recover the data. The clock determines when the data should be sampled by a receiver""s circuits.
The clock may transition at the beginning of the time the data is valid. The receiver would prefer, however, to have a signal during the middle of the time the data is valid. Also, the transmission of the clock may degrade as it travels from its transmission point. In both circumstances, a delay locked loop, or DLL, can regenerate a copy of the clock signal at a fixed phase shift from the original.
FIG. 1 shows a section of a typical computer system component (10). Data (22) that is xe2x80x98nxe2x80x99 bits wide is transmitted from circuit A (20) to circuit B (40). To aid in the recovery of the transmitted data, a clock composed of a clock signal (30), or CLK, is also transmitted with the data. The circuits could also have a path to transmit data from circuit B (40) to circuit A (20) along with an additional clock (not shown). The clock signal (30) may transition from one state to another at the beginning of the data transmission. Circuit B (40) requires a signal temporally located some time after the beginning of the valid data. Furthermore, the clock signal (30) may have degraded during transmission. The DLL has the ability to regenerate the clock signal (30) to a valid state and to create a phase shifted version of the clock to be used by other circuits, for example, a receiver""s sampling signal. The receiver""s sampling signal determines when the input to the receiver should be sampled.
The DLL must delay an output signal versus an input signal by a known phase shift. The entire cycle of a signal is considered a 360 degree phase shift. By specifying a phase shift delay, the same relative delay is specified; however, the absolute amount of delay may be different. For example, a 100 MHz clock signal has a 10 ns cycle time; therefore, a phase shift of 360 degrees would indicate that an entire cycle, or 10 ns, of delay has been added. A 30 degree phase shift is approximately 0.833 ns. A 200 MHz clock signal has a cycle time of 5 ns. A 30 degree phase shift is approximately 0.417 ns. The phase shifts in these examples are the same; however, the temporal delays are not.
In FIG. 2, a DLL (50) is composed of three basic components: a delay element (52), a buffer circuit (54), and a phase detector and delay control (60). The delay element (52) generates a delayed signal (53) that is delayed relative an input signal (30). For this example, the input signal (30) is CLK. The phase detector and delay control (60), or phase adjustment device, controls the amount of delay generated by the delay element (52) based on the phase difference between the input signal (30) and a buffered output signal (55). The buffer circuit (54) takes the delayed signal (53) from the delay element (52) and buffers the delayed signal (53) to any circuits that must receive a buffered output signal (55), such as a receiver""s sampling signal. By buffering the output signal (53), the characteristics of the delay element (52) are not changed due to the capacitive and/or resistive load on the delayed signal (53).
According to one aspect of the present invention, a delay locked loop comprises a delay element that outputs a delayed signal that is delayed relative to an input signal, a differential push/pull buffer adapted to receive the delayed signal to generate a buffered output signal, and a phase adjustment device operatively connected to the delay element to adjust the delay of the delay element based on a phase difference between the input signal and the buffered output signal.
According to another aspect, an integrated circuit comprises a delay locked loop that comprises a delay element that outputs a delayed signal that is delayed relative to an input signal, a differential push/pull buffer adapted to receive the delayed signal to generate a buffered output signal, and a phase adjustment device operatively connected to the delay element to adjust the delay of the delay element based on a phase difference between the input signal and the buffered output signal.
According to another aspect, a delay locked loop comprises delaying means for delaying an input signal and outputting a delayed signal, buffering means for buffering the delayed signal and outputting a buffered output signal, and adjusting means for adjusting a degree of delay of the delaying means based on a phase difference between the input signal and the buffered output signal.
According to another aspect, a method for generating a sampling clock comprises inputting a clock signal to a delay element; generating a delayed clock signal that is delayed relative to the clock signal; inputting the delayed clock signal to a differential push/pull buffer; and buffering the delayed clock signal to generate a buffered clock signal.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.